1. Technical Field
The present invention relates to a semiconductor device, and in particular relates to a semiconductor device having a stack contact, in which a plurality of plugs are stacked.
2. Related Art
Typical conventional technologies related to semiconductor devices having a stack-type dynamic random access memory (DRAM) capacitor includes technologies disclosed in Japanese Patent Laid-Open No. 2002-203,812, Japanese Patent Laid-Open No. 2002-353,334 and Japanese Patent Laid-Open No. 2003-23,111. Among these, Japanese Patent Laid-Open No. 2002-203,812 discloses a technology of forming contact holes of a stacked structure in a semiconductor device, which compatibly contains DRAM cell and a logic embedded therein.
On the other hand, Japanese Patent Laid-Open No. 2002-353,334 discloses a semiconductor device that compatibly contains a DRAM region and a logic region embedded therein. Japanese Patent Laid-Open No. 2002-353,334 also discloses a condition, in which some misalignment is caused when a connecting hole is formed to reach a diffusion layer of the DRAM region.
Besides, Japanese Patent Laid-Open No. 2003-23,111 discloses a semiconductor device that simultaneously has a DRAM memory cell unit and a logic static random access memory (SRAM) embedded therein.
In such stack type semiconductor devices including a DRAM capacitor, a connecting plug extending through a capacitor-forming layer and an interlayer insulating film disposed above the capacitor-forming layer may be possibly formed. For example, when a bit line connecting plug is formed above the DRAM cell, a stack contact, which is configured to have stacked plurality of connecting plugs serving as the bit line connecting plugs, is employed. In addition, a stack contact extending from the semiconductor substrate to the above of the DRAM capacitor may be possibly formed in a peripheral circuit of the DRAM.
In addition, in the device that compatibly contains a DRAM region and a region of the other device, a stack contact having a geometry that is substantially the same as a geometry of a bit line connecting plug may often be provided in the region of the other device. For example, such configuration is adopted for the logic region described in Japanese Patent Laid-Open No. 2002-353,334 as described above.
However, the present inventor has investigated and found problems. A progressing miniaturization of devices requires a reduced space between the stack contacts, and in such environment, a stable formation may be often difficult, when a plurality of connecting plugs that extends through a capacitor-forming layer and an interlayer insulating film disposed thereon are formed to be arranged in mutually adjacent relationship.
The following aspects have been found for the reasons of such problem. In the conventional devices, the stack contacts are formed by stacking the underlying plug constituting the stack contact and the upper layer plug constituting the stack contact, both of which have the same layout.
However, in general, the thickness of the interlayer insulating film is larger than the thickness of the underlying layer in a DRAM capacitor-forming layer. Thus, when the DRAM capacitor-forming layer is included, and a connecting plug extending beyond the DRAM capacitor-forming layer is formed, the connecting hole is required to be deeper. In addition, the connecting hole tends to have a larger diameter in the upper surface of the interlayer insulating film, in order to improving a filling-ability of an electrically conducting material. When a miniaturization is further progressed, it is concerned that such problem may leads to cause a short circuit between adjacent connecting plugs.
While the devices having the DRAM capacitor have been illustrated in the above description, similar problems may also be occurred when a relatively bulky element such as a capacitor and the like is formed in an interlayer insulating film. In other words, since a thickness of the interlayer insulating film is increased in a region for forming a relatively bulky element, it may often be difficult to form a pair of adjacent connecting plugs extending beyond such interlayer insulating film to the upper layer thereof.
To solve the problem, further investigations of the present inventor have eagerly been performed for achieving a stable formation of a plurality of stacked contacts in adjacent locations, so that the present invention is achieved.